This invention relates to integrated circuit device packaging.
A conventional leadframe semiconductor die package has a semiconductor die mounted onto and electrically connected to a leadframe. The leadframe, which may be formed by patterning a sheet of electrically conductive metal such as copper, typically includes a die paddle, onto which the die is affixed, and leads, to which the die is electrically connected. The mounted die may be encapsulated or molded, and the leads may project from one or more sidewalls of the molding or encapsulation (a “leaded package”); or the leads may end at one or more of the sidewalls of the molding or encapsulation (a “leadless package”).
An encapsulated leadless package is shaped generally as a thin rectangular parallelepiped having larger rectangular or square upper and lower sides. Typically, lower surfaces of the die paddle and leads are exposed at the lower side of the package, and end surfaces of the leads are exposed at (and are generally flush with) one or more sidewalls of the package. Thus a typical leadless semiconductor die package appears on the surface as a thin rectangular or square solid block of the molding or encapsulation material, with die paddle surfaces exposed flush with the “underside” of the package and leads exposed flush with the underside and with one or more of the sidewalls of the package adjacent the lower edges. A quad flat no lead (“QFN”) package has leads exposed flush with the sidewalls adjacent all four lower edges, and a dual flat no lead (“DFN”) package has leads exposed flush with the sidewalls adjacent two (typically opposite) lower edges.
In a conventional leadframe package the die may be electrically connected by wire bonds or by flip-chip interconnection.
In a wire-bonded leadframe package the die is affixed “die-up”, that is, oriented so that the active side of the die faces away from the leadframe, and in such a package the die is electrically connected to the leads by wires connecting interconnect pads on the die with bond sites on the leads. Wire bonding requires that the package have both a significantly greater thickness than the die, because of the wire bond “loop height”, and a significantly greater footprint, because of the “wire span”. Additionally, although two or more die may be stacked one over another in a wire bonded leadframe package, where an upper die in a stack of wire bonded die overlaps the interconnect pads of an underlying die, a spacer must be interposed between the die to accommodate the wire loops on the underlying die. This adds still further package thickness, and additional processing steps.
In a flip-chip leadframe package the die is mounted “die-down”, that is, oriented so that the active side of the die faces toward the leadframe, and in such a package the die is electrically connected to the leads by solder bumps or so-called “stud bumps” interposed between the die pads and the bond sites on the leads. Flip-chip interconnect can provide a smaller footprint than a wire bonded comparably dimensioned die, but stacking of flip chip die is impractical.